Tag: Intel MIC
Test-driving Intel Xeon Phi coprocessors with a basic N-body simulation
Colfax International published interesting whitepaper: Intel Xeon Phi coprocessors are capable of delivering more performance and better energy efficiency than Intel Xeon processors for certain parallel applications. In this paper, Andrey Vladimirov of Stanford University and Vadim Karpusenko of Colfax International, investigate the porting and optimization of a test problem for the Intel Xeon Phi…
Colfax Developer Training: Parallel Programming for Intel Xeon Phi Coprocessors
Colfax Developer Training (CDT) will discuss the applicability of the Intel many-core technology, demonstrate the programming models for Intel Xeon Phi coprocessor including native execution and offload-based approaches, and provide extensive optimization techniques.
Nvidia: Examining The Threat From Intel’s Xeon Phi
Intel is a fierce player and represents the first legitimate competitive threat that Nvidia has seen in the space. I believe, however, that Intel’s competitive position in this nascent field is overstated in the near- to medium-term and that expanding TAM and strong leadership from Nvidia’s team should ensure that the segment’s sales and profitability continue to grow, even if Intel gets a piece of the action.
OpenCL 1.2 support for Intel Xeon Phi coprocessor
Intel is extending open standards support to include OpenCL 1.2 for Intel Xeon Phi coprocessors. OpenCL broadens the parallel programming options from Intel and allows developers to maximize parallel application performance on Intel Xeon Phi coprocessors.
Intel previews Xeon Phi details at Hot Chips
Intel has broke its silence on its forthcoming Xeon Phi processor which is supposed to hit the shops later this year. They provided the first look inside its Xeon Phi processor in a Hot Chips talk by George Chrysos, chief architect of Knights Corner.
2nd International Conference on High Performance Computing 2012, Kyiv, Ukraine
National Technical University of Ukraine “Kyiv Polytechnic Institute” and V.M. Glushkov Institute of Cybernetics of NAS of Ukraine are pleased to announce the 2nd International Conference on High Performance Computing (HPC-UA 2012) being held in Kyiv, Ukraine
ispc: A SPMD Compiler with Xeon and Xeon Phi support
ispc is an R&D compiler for a C-based language that is targeted for exploring the performance available from doing SPMD computation on SIMD units found on CPUs and on Intel Xeon Phi coprocessors (using the Intel Many Integrated Core (MIC) architecture).
Intel Xeon Phi Coprocessor Infographic
To complement announcement of Xeon Phi Coprocessor Intel posted fantastic infographic.
Intel announces Xeon Phi coprocessor based on Many Integrated Core (Intel MIC) Architecture
Intel just announced its new brand for “Many Integrated Core Architecture” chips, Intel Xeon Phi, with the coprocessors for workstations, data centers and even supercomputers. Available by the end of 2012, the first generation of Intel Xeon Phi product family will complement the existing Intel Xeon.
TACC-Intel Highly Parallel Computing Symposium in Austin
The TACC-Intel Highly Parallel Computing Symposium will take place on April 10th and 11th 2012 at the Texas Advanced Computing Center (TACC) in Austin, TX.
