Unified Processing Unit (UPU): A next-generation of CPU architecture?
New CPU architectures don’t come along very often — which is why more details on the Harmony Unified Processing Architecture being built by developer ICube are so interesting. Historically, instruction set architectures (ISAs) are risky bets. Not only are they exceptionally difficult to design, it takes an enormous additional effort to create tools that can leverage new capabilities. Even then, companies face an uphill fight to persuade vendors and software developers to recompile existing software to take advantage of the new design.
ICube is founded by Silicon Valley veterans (Simon Moy, CTO was Principal Engineer at NVIDIA and Fred Chow, is Chief Scientist was Chief Scientist at SGI and principle engineer at MIPS) who are experts in processor, software and integrated circuit development, the strength of our engineering team enjoys international distinction. The company is based in China. Details on ICube’s silicon are still limited, but the expertise of the two men helps shed a bit of light on what the chip looks like.
The Harmony Unified Processing Architecture (and the first iteration of that architecture, the IC1) are described as consisting of “the Multi-Thread Virtual Pipeline parallel computing core (MVP), an independent instruction set architecture, an optimizing compiler, and the Agile Switch dynamic load balancer.” Elsewhere, the chip is described as a “parallel computing stream processor core.” We also know, based on available literature, that the chip uses both SMP (Symmetric Multi-Processing) and SMT (Simultaneous Multi-Threading).
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The Harmony Unified Processor Technology sets a new industry standard of performance by processing up to four threads (tasks) in each core. This contrasts with existing cores in the market that are limited to a single thread per core.
VR-Zone describes the chip as an “elegant 32-bit RISC core, not unlike the original MIPS.” The IC1 implements 4-way SMT; each core can operate on up to four threads. The UPU approach means that execution resources, memory space, and register data is shared across the entire chip — there’s no such thing as a “CPU workload” versus a “GPU workload.”
The IC1 is designed for handheld and mobile devices and runs Android. The company’s efforts in this area could be seen as the “other” arm of China’s initiative to develop its own competitive CPU architectures. Much of the research to date has focused on the country’s Loongson/Godson-3 processors, which can be found in China’s homegrown supercomputers, but these are chips intended for mainstream PC form factors and homegrown supercomputers. ICube’s IC1 gives China a homegrown alternative for building its own phones and devices rather than being beholden to foreign companies for hardware.
[via ExtremeTech, VR-Zone and ICube]
Category: News
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