To followup NVIDIA’s CEO Jen-Hsun Huang Keynote at SC11. We would like to share more technical and insightful presentation by Dr. William J. Dally Bell, professor of Engineering, Stanford University and Chief Scientist, NVIDIA Corporation. In the keynote Jen-Hsun Huang emphasized the power bottleneck of the current CPUs. Nvidia is a story of “low end” Disruptive Innovation originated from video gaming industry. Can GPUs, after crossing the barrier of “low end” innovation, stay on the curve of sustaining innovation and bring exascale performance per 20mw of power?
ISTeC Distinguished Lecture in conjunction with the Electrical and Computer Engineering Department and Computer Science Department Seminar Series presents From Cellphones to Supercomputers: Energy-Efficient Computing. It has been delivered on Monday, Oct. 24.
From Cellphones to Supercomputers: Energy-Efficient Computing
Cell phones and supercomputers, the two extremes of the computing space, are both power limited. Their performance is limited not by the number of arithmetic units that can be fit on a chip, but rather by the power consumed by each arithmetic unit. A high-performance processor today consumes about 2nJ per operation.
Evolution of both cell phones and supercomputers requires that we reduce this number to about 20pJ per operation. Only 3-4x of this 100x reduction is expected to come from improved semiconductor technology. The remainder must come from reduction of overhead and enhanced locality.
This talk will discuss the challenges of energy-efficient computing and some of the potential solutions to this problem.
Speculative Reservation Flow-Control: An Efficient Congestion Control Mechanism
Congestion caused by hot-spot traffic can significantly degrade the performance of a computer network. In this talk I describe the Speculative Reservation Protocol (SRP), a new network congestion control mechanism that relieves the effect of hot-spot traffic in high bandwidth, low latency, lossless computer networks.
Compared to existing congestion control solutions, such as Explicit Congestion Notification (ECN), that react to network congestion through packet marking and rate throttling, SRP takes a proactive approach of congestion avoidance. Using a light-weight endpoint reservation protocol and speculative packet transmission, SRP ensures a hot-spot congestion free network while creating minimum overhead.
Our simulation results show that SRP responds more rapidly to the onset of severe hot-spots than ECN and creates less impact on the latency and throughput of background traffic. SRP also performs comparable to networks without congestion control on benign traffic patterns by reducing the latency and throughput overhead commonly associated with reservation protocols.
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William Dally is the Willard R. and Inez Kerr Bell Professor of Engineering at Stanford University and Chief Scientist at NVIDIA Corporation. Bill and his group have developed system architecture, network architecture, signaling, routing, and synchronization technology that can be found in most large parallel computers today. While at Bell Labs, Bill contributed to the BELLMAC32 microprocessor and designed the MARS hardware accelerator. At Caltech, he designed the MOSSIM Simulation Engine and the Torus Routing Chip which pioneered wormhole routing and virtual-channel flow control.
While a professor of Electrical Engineering and Computer Science at the Massachusetts Institute of Technology, his group built the J-Machine and the M-Machine, experimental parallel computer systems that pioneered the separation of mechanisms from programming models and demonstrated very low overhead synchronization and communication mechanisms. At Stanford University, his group has developed the Imagine processor, which introduced the concepts of stream processing and partitioned register organizations. Bill has worked with Cray Research and Intel to incorporate many of these innovations in commercial parallel computers, with Avici Systems to incorporate this technology into Internet routers, co-founded Velio Communications to commercialize high-speed signaling technology, and co-founded Stream Processors, Inc. to commercialize stream processor technology.
He is a member of the National Academy of Engineering, a Fellow of the IEEE, a Fellow of the ACM, and a Fellow of the American Academy of Arts and Sciences. He has received numerous honors including the ACM Eckert-Mauchly Award, the IEEE Seymour Cray Award, and the ACM Maurice Wilkes Award. He currently leads projects on computer architecture, network architecture, and programming systems. He has published over 200 papers in these areas, holds over 75 issued patents, and is an author of the textbooks, Digital Systems Engineering and Principles and Practices of Interconnection Networks.