GTC2013

Design Methods and Tools for FPGA-Based Acceleration of Scientific Computing

| 7 November, 2011

http://research.microsoft.com/en-us/um/cambridge/events/date2011/

Date: Fri, 2011-03-18
Organisers:
  • Dr George A Constantinides, Imperial College, UK
  • Prof Brent Nelson, Brigham Young University, US
  • Prof Satnam Singh, Microsoft Research, UK

Description:  Field-Programmable Gate Arrays (FPGAs) have been considered as possible implementation platforms for computation since the early 1990′s.  Over the technology generations, the regularity of FPGA designs has allowed them to stay at the leading edge of each new technology node, with architectural innovations enabling their widespread adoption for embedded applications.  The potential of FPGAs for scientific computations is well understood today; nonetheless, long implementation cycles have hindered their faster adoption for numerically intensive scientific applications.  We currently stand on a threshold, where various key research contributions and initiatives have the potential for propel FPGA-based computation from the embedded space into scientific computing.  At the same time, other “accelerator technologies” such as GPGPU are beginning to make deep inroads into traditional HPC, with the potential for common design capture languages such as OpenCL.

This workshop will critically examine the state of the art in this community, and will include a panel discussion of whether FPGAs will ever make a significant breakthrough into scientific computation, and the challenges – technological and otherwise – that will need to be surmounted for them to do so.  We aim to bring together the leading researchers in the field to help converge on collaborative research programming enabling this vision.

The workshop programme contains the following elements:

  • Six sessions with in total four regular presentations
  • Two poster sessions
  • A panel session

Final Programme:

0845 SESSION 1: OPENING AND PAPER
Moderator: Satnam Singh – Microsoft Research, UK
0900 Higher Level Programming Abstractions for FPGAs using OpenCL
Desh Singh Altera, CA
1000 SESSION 2: COFFEE AND POSTERS
1045 SESSION 3: PANEL: DISCUSSION
“FPGA-based Scientific Computing: A Bright Future?”
Moderator:George A. Constantinides-Imperial College, UK
Panelists:
Brent Nelson – Brigham Young University, US
Satnam Singh – Microsoft Research, UK
Greg Stitt – University of Florida, US (slides)
David Thomas – Imperial College, UK
1200 LUNCH BREAK
1300 SESSION 4: PAPERS
Moderator: Brent Nelson – Brigham Young University, US
1300 Execution of a Computational Fluid Dynamics application on FLOPS-2D, a multi-FPGA platform
Hideharu Amano – Keio University, JP
1400 Exploiting spatial parallelism to improve both speed and accuracy in financial computing
David Thomas – Imperial College, UK
1500 SESSION 5: COFFEE AND POSTERS
1545 SESSION 6: PAPER
Moderator: David Thomas – Imperial College, UK
1545 Floating Point Vector Processing on an FPGA
Miriam Leeser – Northeastern University, US
1645 CLOSE

Poster Session (please click on links for abstracts):

  1. L. Pomante, “Dedicated Architectures for Scientific Computing: An HW/SW Co-Design Approach“
  2. G. Huong and S. Kim, “GCC Compiler as High-level Language to Hardware Description Language Translator“
  3. M. Koester, J. Hagemeyer, F. Margaglia, M. Porrmann, F. Dittmann, M. Ditze, L. Sterpone, J. Harris, and J. Ilstad, “Design Flow for a Fault-Tolerant Reconfigurable Multi-FPGA Architecture for Space Applications“
  4. Maache, T. Nechma, M. Zwolinski, and J. Reeve, “Accelerating SPICE Algorithms on FPGAs“
  5. P. Zhu, R.C.C. Cheung, H. Li, L. Cui, and B. Hu, “FPGA-based Acceleration for Graph Similarity“
  6. J. Hoffmann, F. Guettler, and M. Bogdan, “Design of Electronic Systems by Dynamic Instruction Sets for Reconfigurable Hardware using High-Level OpenCL-C“
  7. Yu, D.Z. Wang, R.C.C. Cheung, and H. Yan, “An FPGA-based Geometric Biclustering Accelerator for Genes Microarray Data Analysis“
  8. L. Cui, J. Chen, and B. Hu, “Acceleration of Multi-Agent Simulation based on FPGA“
  9. Akagic and H. Amano, “Multiple Table Lookup Implementation of Error Correction on an FPGA“
  10. M. Roessler, D. Fross, J. Langer, and U. Heinkel, “FPGA-Accelerated Exploration of Monte Carlo Simulations Using High-Level Design Methodology“
  11. Boland and G. Constantinides, “Bounding Variable Values and Round-off Effects using Handelman Representations“
  12. S. Bayliss and G. Constantinides, “Designing Application-Specific SDRAM Memory Systems using Parametric Integer Linear Programming”
  13. S. Ahmed and J. Serot and F. Berry, “An Actor-based High-level Language for Implementing Stream-processing Applications on Reconfigurable Hardware“
  14. J. Romoth, J. Hagemeyer, M. Porrmann, and U. Rueckert, “Fast Design-Space Exploration with FPGA Clusters“
  15. R. Chaimberlain, “Using FPGAs and High Level Languages to Exploit the Inherent Parallelism of Multi-Dimensional FFTs“
  16. P. Coussy and D. Heller, “GAUT – A Free and Open Source High-Level Synthesis Tool for FPGA-based Acceleration of Scientific Computing“
  17. P. Echeverria and M. Lopez-Vallejo, “FPGA Acceleration of Monte Carlo-based Financial Simulation: Design Challenges and Lessons Learnt“
  18. S. Carrillo, J. Harkin, L. McDaid, and F. Morgan, “Advances in Scalable, Adaptive Interconnect for Reconfigurable Bio-Inspired Computational Platforms“
  19. M. Gorev, V. Pesonen, D. Mihhailov, M. Jenihhim, and P. Ellervee, “FPGA-Based Implementation of EEG Analyzer“
  20. Z. Chen, X. Guo, A. Sinha, and P. Schaumont, “System Level Verification and Performance Analysis for FPGA Accelerated Computers“
  21. N.C. Audsley, “Challenges of Multi-FPGA Development“
  22. T. Miyajima, H. Amano, and M. Arai, “An FPGA Implementation of Face Angle Detection System for Automobile using Impulse C“
  23. Koch, C. Beckhoff, and J. Torresen, “How Partial Reconfiguration Can Help HPC“
  24. K. Inakagata, H. Morishita, Y. Osana, N. Fujita, and H. Amano, “Design of ALU Array Based Dataflow Machine for Multi-FPGA System“
  25. Yu, T. Mak, X. Li, F. Xia, A. Yakovlev, and Y. Sun, “Reconfigurable Streaming Kernels for Multichannel Neurophysiological Recording Systems“
  26. Yalamarthy, J. Coburn, and R.K. Gupta, “Computational Mass Spectrometry in a Reconfigurable Coherent Coprocessing Architecture“
  27. Cilardo, “Exploring the Potential of Hardware Reconfigurability for Cryptanalytic Applications“
  28. Goehringer, M. Birk, M. Huebner, and J. Becker, “High-Level Design for FPGA-based Multiprocessor Accelerators“
  29. S.A. Ostadzadeh and K. Bertels, “QUAD: A Sophisticated Memory Access Profiling Toolset“

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Category: Computer Science, Training & Events

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